1. Field of the Invention
The invention relates to a method for testing printed circuit boards, wherein the circuit boards are brought into contact with conducting test-contact elements at certain contact points which are connected to the conductor tracks, wherein the test-contact elements or a partial number thereof are connected, in succession in clock-pulsed manner according to a certain test program, to a source of test voltage and wherein during each test clock pulse the test current flowing via the test-contact elements or a parameter related thereto is measured.
2. Description of the Related Art
The contact points on circuit boards serve to make contact with electronic components and are, as a rule, arranged in a definite grid. The test-contact elements are also set in accordance with this grid. Said test-contact elements may be realised by means of test pins, but they may also be realised in some other way, for example by means of an elastic layer of rubber which rests on the circuit board and which is provided with graphite-bead inserts. Said rubber layer is conducting at the contact points if it is pressed together at these points.
As a result of the tendency to make electronic components smaller and smaller and to increase the packaging density, with respect to circuit boards there is also a requirement to set the grid of the contact points so as to make them closer and closer together. Although, as a result, the circuit boards that are intended for use in electrical appliances are, as a rule, becoming smaller in their dimensions, this reduction is size is utilised optimally in the course of manufacture in such a way that several basic patterns or panels are provided on an initial circuit board. The initial circuit board is tested as a unit and is only separated into single elements later.
The ever increasing density of contact points on circuit boards to be tested has the consequence that the number of measurements to be carried out in the course of testing is becoming correspondingly larger.
Great efforts have been made hitherto to shorten, to an ever more acute degree, the mechanical time for the interchange of circuit boards to be tested. The constructional provision for the purpose of realising short interchange-times has meanwhile become considerable. From this point of view it is unsatisfactory if the ratio of the measuring-time to the interchange-time keeps on increasing, so that the cycle time resulting from the sum of the two times is ultimately substantially determined by the measuring-time, and the technical provision for the purpose of shortening the interchange-time no longer seems justified.
The object underlying the invention is therefore to shorten the measuring-time.
Proceeding from the method described at the outset, the solution consists in subdividing the circuit boards into a plurality of test areas, each of which contains only a partial number of contact points, and in all or at least some of the test areas being tested in parallel.
To the extent that the initial circuit board has been conceived in a multiple panel, it makes sense to provide a number of test areas that is equal to the number of panels, with each test area containing the conductor tracks of one panel. An example of this is shown in FIG. 1. An advantage in this case is the fact that the measuring-time is of equal length for all panels. Each test area can be tested, for example, in such a way that the contact points bounding a conductor track are connected in succession in clock-pulsed manner to the test-voltage source, and it is established by measurement of the flow of current whether the conductor tracks possibly exhibit an interruption fault. After this, in each instance a contact point, on the one hand, and all the remaining contact points that are not connected to this contact point by a conductor track, on the other hand, are connected in succession in clock-pulsed manner to the test-voltage source, in order to establish whether the conductor track that is connected to the contact point possibly has an undesirable contact with other conductor tracks and to this extent exhibits an insulation fault. As an alternative to this, it is also possible to test a panel firstly for interruption faults in the course of the parallel testing and to begin the testing for insulation faults in the course of testing another panel.
It is by no means necessary for the test areas to be laid down in such a way that they contain only conductor tracks extending within these test areas. Instead, the boundaries of the test areas can also be laid down in such a way that they pass straight through conductor tracks, so that the conductor tracks are, to a certain extent, area-overlapping. This is useful in particular when the boundary of the panel extends in the same way and the area-overlapping conductor tracks are likewise separated after separation of the initial circuit board into individual panels. An example of this is shown in FIG. 4. But care has to be taken here to ensure that in the course of the parallel testing the area-overlapping conductor tracks do not have test voltage applied to them simultaneously from both sides. This can be guaranteed by an appropriate design of the test program (algorithm). Normally it is also possible to dispense with testing such area-overlapping conductor tracks for interruption faults, sincexe2x80x94as already mentionedxe2x80x94the conductor tracks are separated in any case.
The teaching according to the invention is by no means tied to laying down the area boundaries always in conformity with the boundaries of the panel. Rather it is to be understood in all generality and may also find application when a circuit board to be tested has merely a high contact-point density without a basic pattern being repeated several times in the form of panels.
The invention further relates to a device for implementing the method described above. The device has to contain, in known manner, a plurality of test-contact elements intended for contacting the contact points of the conductor tracks, furthermore a source of test voltage, program control means, variable connecting means that are capable of being switched over by the program control means in such a way that the test-contact elements are connected individually or in groups, in succession in clock-pulsed manner according to a certain test program, to the test-voltage source and evaluating means that measure and evaluate the flow of current through the test-contact elements or a parameter related thereto.
In order to be able to realise parallel measurements of the individual test areas, in accordance with the invention at least some of the hardware described above has to be multiplied so as to correspond to the number of test areas. In practice this means that at least the evaluating means for implementing a parallel testing of test areas have to be provided in multiple number.
Overall, with reference to the parallel testing it is to be noted that the following two conditions have to be satisfied:
1. The tests have to be undertaken independently of one another, and one testing operation must not have to wait for the result of the other testing operation. In other words, this means that the result of measurement of one test area must not be a basis for the measurement in another test area.
2. The same resources must not be used for the parallel testing. In practice this means that the hardware that is necessary for the measurement or evaluation has to be available in multiple configuration.
With a view to implementing the method according to the invention there is also the possibility of realising the individual test areas by means of test modules which are arranged side by side in known manner, as described in EP-B1 0 108 405 for example. The starting-point for the state of the art according to this patent specification is that the possessor of a testing device is able to extend his test bench arbitrarily by additional purchase of modules. The concept of causing the modules to operate autonomously in parallel is not present in this printed publication. Rather they are intended to operate together like a single large module in such a manner that it is possible to perform a test between very remote test points, even in the case of very large circuit boards.
Proceeding from the state of the art as described above, a device having several test modules arranged side by side is accordingly known for testing printed circuit boards, each of said test modules being connected to a plurality of conducting test-contact elements that are capable of being connected with contact points on the circuit boards in accordance with a certain test program.
If the inventive idea of parallel testing as elucidated above is applied to this known device, this results in the teaching to design the test program in such a way that the test modules test the test areas of the circuit boards assigned spatially to them simultaneously and independently of one another.